1. Field of the Invention
The present invention relates to a method of reading stored data and a semiconductor memory device, more particularly relates to a method of reading data stored in a semiconductor memory device including a static type random access memory (RAM) and such a semiconductor memory device and to a semiconductor memory device including a static type content addressable memory (CAM).
2. Description of the Related Art
First, an explanation will be made of a static RAM (SRAM) and a CAM having a SRAM type memory circuit.
(SRAM)
SRAMs enable high speed read and write operations and, at the same time, eliminate the need for a refresh operation of the stored data as with a dynamic RAM (DRAM) and enable streamlining of peripheral circuits. Due to these advantages, they are being widely used as cache memories, memories of portable terminals, and other relatively small capacity memory devices for which high speed operation and streamlining are required.
As basic configurations of a memory cell of an SRAM (hereinafter referred to as an xe2x80x9cSRAM cellxe2x80x9d), a six-transistor type SRAM cell using six transistors and a four-transistor type SRAM cell omitting the load transistors of this six-transistor type SRAM cell are generally known.
First, an explanation will be made of the six-transistor type SRAM cell.
FIG. 23 is a circuit diagram of a six-transistor type SRAM cell. The SRAM cell shown in FIG. 23 has an n-type MOS transistor Qn1a to n-type MOS transistor Qn1d and a p-type MOS transistor Qp1a and p-type MOS transistor Qp1b. 
Drains of the p-type MOS transistor Qp1a and the n-type MOS transistor Qn1c are connected to a node N1a, while their gates are connected to a node N1b. Also, a source of the p-type MOS transistor Qp1a is connected to a power supply voltage Vcc, while the source of the n-type MOS transistor Qn1c is connected to a reference potential. These p-type MOS transistor Qp1a and n-type MOS transistor Qn1c form one CMOS inverter using the node N1b as an input and using the node N1a as an output.
The drains of the p-type MOS transistor Qp1b and the n-type MOS transistor Qn1d are connected to the node N1b, while their gates are connected to the node N1a. Also, the source of the p-type MOS transistor Qp1b is connected to the power supply voltage Vcc, while the source of the n-type MOS transistor Qn1d is connected to the reference potential. These p-type MOS transistor Qp1b and n-type MOS transistor Qn1d form one CMOS inverter using the node N1a as an input and using the node N1b as an output.
The inputs and outputs of the CMOS inverter comprised by the p-type MOS transistor Qp1a and the n-type MOS transistor Qn1c and the CMOS inverter comprised by the p-type MOS transistor Qp1b and the n-type MOS transistor Qn1d are connected to each other in the form of a ring, whereby one memory circuit is comprised.
The gate of the n-type MOS transistor Qn1a is connected to a word line WORD, its drain is connected to a bit line BIT, and its source is connected to the node N1a. 
The gate of the n-type MOS transistor Qn1b is connected to the word line WORD, its drain is connected to an inverted bit line BITB, and its source is connected to the node N1b. 
Next, an explanation will be made of the read operation and the write operation of a six-transistor type SRAM cell having the above configuration.
The stored data of the SRAM cell is stored in the memory circuit by the CMOS inverter in either of a state where the node N1a is at high level and the node N1b is at the low level or a state where the node N1a is at the low level and the node N1b is at the high level. During a period where this stored data is held, the word line WORD is set at the low level, and the n-type MOS transistor Qn1a and the n-type MOS transistor Qn1b are brought to a cutoff state. By this, the memory circuit and the bit line are separated, so the stored data is held.
When reading the stored data of the SRAM cell, the bit line BIT and the inverted bit line BITB are pulled up to the power supply voltage Vcc in advance by a not illustrated pullup circuit. The word line WORD is set to a high level in this state. By this, the n-type MOS transistor Qn1a and the n-type MOS transistor Qn1b become conductive, and the voltage of the bit line BIT or the inverted bit line BITB changes in accordance with the stored data.
For example, when the node N1a is at the high level and the node N1b is at the low level, since the bit line BIT and the node N1a have almost equal voltages, no current flows through the n-type MOS transistor Qn1a and the potential of the bit line BIT remains at the power supply voltage Vcc as it is and does not change, but the inverted bit line BITB has a high voltage in comparison with the node N1b, so the current flows from the inverted bit line BITB to the node N1b and the potential of the inverted bit line BITB falls. The potential difference (or current difference) between these bit line BIT and inverted bit line BITB is amplified by a not illustrated differential amplifier circuit and output to a data line.
When writing the stored data of the SRAM cell, the word line WORD is set at the high level in a state where either of the bit line BIT or the inverted bit line is pulled down to the reference potential and the other is pulled up to the power supply voltage Vcc in accordance with the data to be written. By this, the node N1a and the node N1b are set to potentials in accordance with the write data.
Next, an explanation will be made of a four-transistor type SRAM cell.
FIG. 24 is a circuit diagram of a four-transistor type SRAM cell. The SRAM cell shown in FIG. 24 has an n-type MOS transistor Qn2a, n-type MOS transistor Qn2b, p-type MOS transistor Qp2a, and p-type MOS transistor Qp2b. 
The drain of the n-type MOS transistor Qn2a is connected to a node N2a, its gate is connected to a node N2b, and its source is connected to the reference potential.
The drain of the n-type MOS transistor Qn2b is connected to a node N2b, its gate is connected to a node N2a, and its source is connected to the reference potential.
The gate of the p-type MOS transistor Qp2a is connected to a word line WORDB, its source is connected to the bit line BIT, and its drain is connected to the node N2a. 
The gate of the p-type MOS transistor Qp2b is connected to the word line WORDB, its source is connected to the bit line BITB, and its drain is connected to the node N2b. 
The inputs and outputs of the inverter by the n-type MOS transistor Qn2a and the inverter by the n-type MOS transistor Qn2b are connected to each other in the form of a ring, whereby one memory circuit is comprised. Also, the size of transistors is set so that a leakage current in the off state of the p-type MOS transistor Qp2a and the p-type MOS transistor Qp2b becomes larger than the leakage current of the n-type MOS transistor Qn2a and the n-type MOS transistor Qn2b, charges are supplied from the bit line BIT and the inverted bit line BITB which are pulled up to the power supply voltage Vcc to the node N2a and the node N2b by this, and the stored data of the memory circuit is held constant.
Next, an explanation will be made of a read operation and write operation of a four-transistor type SRAM cell having the above configuration.
The stored data of the SRAM cell is stored in the memory circuit of the two transistors mentioned above in either of the state where the node N2a is at the high level and the node N2b is at the low level or the state where the node N2a is at the low level and the node N2b is at the high level. During the period where this stored data is held, the word line WORDB is set at the high level and the p-type MOS transistor Qp2a and the p-type MOS transistor Qp2b are brought to a cutoff state and, at the same time, the bit line BIT and the inverted bit line BITB are pulled up to the power supply voltage Vcc. As mentioned above, charges are supplied to the node N2a and the node N2b by the leakage current of the p-type MOS transistor Qp2a and the p-type MOS transistor Qp2b, so the stored data of the memory circuits of two transistors is held constant.
When reading the stored data of the SRAM cell, the word line WORDB is set at the low level, the p-type MOS transistor Qp2a and the p-type MOS transistor Qp2b become conductive, and the voltage of the bit line BIT or the inverted bit line BITB changes in accordance with the stored data.
For example, when the node N2a is at the high level and the node N2b is at the low level, since the bit line BIT and the node N2a have almost equal voltages, no current flows through the n-type MOS transistor Qn2a and the potential of the bit line BIT remains at the power supply voltage Vcc as it is and does not change, but the inverted bit line BITB has a high voltage in comparison with the node N2b, so the current flows from the inverted bit line BITB to the node N2b and the potential of the inverted bit line BITB falls. The potential difference (or current difference) between these bit line BIT and inverted bit line BITB is amplified by a not illustrated differential amplifier circuit and output to the data line.
When writing the stored data of the SRAM cell, the word line WORDB is set at the low level in a state where either of the bit line BIT or the inverted bit line BITB is pulled down to the reference potential and the other is pulled up to the power supply voltage Vcc in accordance with the data to be written. By this, the node N2a and the node N2b are set to potentials in accordance with the write data to be written.
Next, an explanation will be made of a CAM.
As a memory having a function capable of processing for search of data at a high speed, an associative memory has been known. An associative memory is also referred to as a content addressable memory (CAM) and has a search function for searching for data from the inside of the memory matching with data input from the outside and outputting the address thereof in addition to the memory functions provided in an usual RAM such as the writing and reading of data.
A CAM enables data for search to be searched for from among all stored data by only a few clocks. Since the search speed is extremely high in comparison with software, CAMs are utilized for various processing for performing high speed data search. CAMs are utilized in a variety of fields, for example, for applications for searching for an IP address cached in the memory in a router, for a translation lookaside buffer (TLB) for converting an address from a virtual address in a virtual memory system to a physical address, for an artificial intelligence machine for pattern recognition of faces, fingerprints, etc., and for compression and decompression of image data.
A CAM has a group of memory cells arranged in a matrix (CAM cell array). Each memory cell thereof has a logical circuit (for example, exclusive OR circuit) for judging a match or mismatch of the search data and the memory data in addition to SRAM type and DRAM type memory circuits.
Also, there are two types of CAMs: a binary CAM storing binary data of a logical value xe2x80x9c1xe2x80x9d or a logical value xe2x80x9c0xe2x80x9d in its memory cell and a ternary CAM storing ternary data of the logical value xe2x80x9c1xe2x80x9d, logical value xe2x80x9c0xe2x80x9d, or logical value xe2x80x9cxxe2x80x9d (don""t care). The logical value xe2x80x9cxxe2x80x9d in the ternary CAM is a value by which the data are always judged to match at the time of search of data.
Below, an explanation will be made of a binary CAM and ternary CAM having SRAM type memory circuits by referring to FIG. 25 to FIG. 27.
FIG. 25 is a circuit diagram of an example of the configuration of a binary CAM cell having an SRAM type memory circuit.
In FIG. 25, the notation Qp1 and notation Qp3 designate p-type MOS transistors, while the notation Qn2 and notation Qn4 to notation Qn9 designate n-type MOS transistors.
In the p-type MOS transistor Qp1 and the n-type MOS transistor Qn2, the drain and source terminals are connected in series between the power supply voltage Vcc and the reference potential with a storage node N1 as the midpoint of connection. Also, both gates are connected to a storage node N2.
In the p-type MOS transistor Qp3 and the n-type MOS transistor Qn4, the drain and source terminals are connected in series between the power supply voltage Vcc and the reference potential with the storage node N2 as the midpoint of connection. Also, both gates are connected to the storage node N1.
In the n-type MOS transistor Qn5, the source and drain terminals are connected between a bit line BL and the storage node N1, and the gate is connected to the word line WL.
In the n-type MOS transistor Qn6, the source and drain terminals are connected between a bit line/BL and the storage node N2, and the gate is connected to the word line WL.
In the n-type MOS transistor Qn7 and the n-type MOS transistor Qn8, the source and drain terminals are connected in series with a node N3 as the midpoint of connection. Also, the gate of the n-type MOS transistor Qn7 is connected to the storage node N2, while the gate of the n-type MOS transistor Qn8 is connected to the storage node N1.
In the n-type MOS transistor Qn9, the gate is connected to the node N3, and the source and drain terminals are connected between a mismatch detection line ML and the reference potential.
Next, an explanation will be made of the operation of the binary CAM cell of FIG. 25 having the above configuration.
The p-type MOS transistor Qp1 and the n-type MOS transistor Qn2 connected in series between the power supply voltage Vcc and the reference potential form one CMOS inverter using the storage node N2 as the input and using the storage node N1 as the output. Similarly, the p-type MOS transistor Qp3 and the n-type MOS transistor Qn4 form one CMOS inverter using the storage node N1 as the input and using the storage node N2 as the output. The stored data of the memory cell is stored in a circuit obtained by connecting these two CMOS inverters in the form of a ring, in either of a state where the storage node N1 is at the high level and the storage node N2 is at the low level or a state where the storage node N1 is at the low level and the storage node N2 is at the high level.
The n-type MOS transistor Qn5 and the n-type MOS transistor Qn6 are transistors for controlling access from the bit line BL and bit line/BL to the storage nodes. While holding the stored data, the word line WL is set at the low level, the storage nodes and the bit line become separated, and the stored data is held constant in this state.
When the stored data of the CAM cell is read out, the bit line BL and the bit line/BL are pulled up to the power supply voltage Vcc in advance by a not illustrated pullup circuit, and the word line WL is set to the high level in this state. By this, the n-type MOS transistor Qn5 and the n-type MOS transistor Qn6 become on, and the voltages of the bit line BL and the bit line/BL fluctuate in accordance with the stored data.
For example, when the storage node N1 is at the high level and the storage node N2 is at the low level, the bit line BL and the storage node N1 have almost equal voltages, so no current flows through the n-type MOS transistor Qn5 and the potential of the bit line BL remains at the power supply voltage Vcc as it is and does not change, but the bit line/BL has a high voltage in comparison with the storage node N2, so current flows from the bit line/BL to the storage node N2 and the potential of the bit line/BL falls. The potential difference (or current difference) of these bit line BL and bit line/BL is amplified by a not illustrated differential amplifier circuit and output to the data line.
When the stored data is written into the CAM cell, the word line WL is set at the high level in a state where either of the bit line BL or the bit line/BL is pulled down to the reference potential and the other is pulled up to the power supply voltage Vcc in accordance with the data to be written. By this, the n-type MOS transistor Qn5 and the n-type MOS transistor Qn6 become on, and the level of the storage node N1 and the storage node N2 is set to the level in accordance with the write data.
When searching for match between the stored data of the CAM cell and the search data, in the holding state of the stored data where the word line WL is set at the low level, either of the bit line BL or the bit line /BL is pulled down to the reference potential in accordance with the value of the search data, and the other is pulled up to the power supply voltage Vcc. Also, the mismatch detection line ML is pulled up to the power supply voltage Vcc by a not illustrated voltage supply circuit.
Here, the match search operation of this binary CAM cell will be explained by concretely showing the search data and the stored data. In the following explanation, assume that the bit line BL is set at the high level and the bit line /BL is set at the low-level when the search data has the logical value xe2x80x9c1xe2x80x9d and that the inverse levels thereto are set in these bit lines when the search data has the logical value xe2x80x9c0xe2x80x9d. Also, assume that the storage node N1 becomes the high level and the storage node N2 becomes the low level when the stored data of the CAM cell has the logical value xe2x80x9c1xe2x80x9d and that levels inverse to those are held in the storage nodes when the stored data has the logical value xe2x80x9c0xe2x80x9d.
For example, when the search data input from the bit line has the logical value xe2x80x9c1xe2x80x9d and the stored data has the logical value xe2x80x9c0xe2x80x9d, the storage node N1 becomes the low level, so the n-type MOS transistor Qn8 becomes off and the storage node N2 becomes the high level, therefore the n-type MOS transistor Qn7 becomes on. Accordingly, a positive charge is supplied from the bit line BL to the node N3 via the n-type MOS transistor Qn7 to charge it to the high level, so the n-type MOS transistor Qn9 becomes on and the mismatch detection line ML becomes the low level.
When the search data has the logical value xe2x80x9c0xe2x80x9d and the stored data has the logical value xe2x80x9c1xe2x80x9d, the n-type MOS transistor Qn7 becomes off and the n-type MOS transistor Qn8 becomes on, and the mismatch detection line ML similarly becomes the low level.
When both of the search data and the stored data have the logical value xe2x80x9c1xe2x80x9d, the storage node N2 becomes the low level, so the n-type MOS transistor Qn7 becomes off and the storage node N1 becomes the high level, therefore the n-type MOS transistor Qn8 becomes on. At this time, since the bit line /BL is at the low level, the node N3 becomes the low level, the n-type MOS transistor Qn9 becomes off, and the mismatch detection line ML becomes the high level.
When both of the search data and the stored data have the logical value xe2x80x9c0xe2x80x9d, the n-type MOS transistor Qn7 becomes on and the n-type MOS transistor Qn8 becomes off. At this time, the bit line BL is at the low level, so the node N3 becomes the low level and the mismatch detection line ML similarly becomes the high level.
In this way, the mismatch detection line ML becomes the low level when the stored data and the search data do not match, while it becomes the high level when the stored data and the search data match. Also, one type of NOR circuit is formed by a common mismatch detection line ML and n-type MOS transistors Qn9 of a plurality of CAM cells connected in parallel to this. If there is even one CAM cell wherein the stored data and the search data do not match in these plurality of CAM cells, the common mismatch detection line ML becomes the low level. Accordingly, by only searching for a high level mismatch detection line ML from among all mismatch detection lines ML of the CAM cell array, the address of the stored data matching with the search data can be searched for from among all stored data.
This completes the explanation of operation of the binary CAM cell shown in FIG. 25.
FIG. 26 is a circuit diagram of an example of another configuration of a binary CAM cell having the SRAM type memory circuit. The difference from the binary CAM cell shown in FIG. 25 lies in the logical circuit portion for outputting the match search result.
In FIG. 26, notation Qp10 and notation Qp12 designate p-type MOS transistors, notation Qn11 and notation Qn13 to notation Qn18 designate n-type MOS transistors, notation WL designates the word line, notation BL and notation/BL designate a pair of bit lines, and notation ML designates the mismatch detection line.
In the p-type MOS transistor Qp10 and the n-type MOS transistor Qn11, the drain and source terminals are connected in series between the power supply voltage Vcc and the reference potential with a storage node N4 as the midpoint of connection. Also, both of their gates are connected to a storage node N5.
In the p-type MOS transistor Qp12 and the n-type MOS transistor Qn13, the drain and source terminals are connected in series between the power supply voltage Vcc and the reference potential with the storage node N5 as the midpoint of connection. Also, both of their gates are connected to the storage node N4.
In the n-type MOS transistor Qn14, the source and drain terminals are connected between the bit line BL and the storage node N4, while the gate is connected to the word line WL.
In the n-type MOS transistor Qn15, the source and drain terminals are connected between the bit line /BL and the storage node N5, while the gate is connected to the word line WL.
In the n-type MOS transistor Qn16 and the n-type MOS transistor Qn17, the source and drain terminals are connected in series between the bit line BL and the bit line /BL with a node N6 as the midpoint of connection. Also, the gate of the n-type MOS transistor Qn16 is connected to the storage node N4, while the gate of the n-type MOS transistor Qn17 is connected to the storage node N5.
In the n-type MOS transistor Qn18, the gate is connected to the node N6, and the source and drain terminals are inserted in series on the mismatch detection line ML.
Next, an explanation will be made of the operation of the binary CAM cell of FIG. 26 having the above configuration.
In the same way as the binary CAM cell of FIG. 25, the p-type MOS transistor Qp10 and n-type MOS transistor Qn11 form one CMOS inverter, the p-type MOS transistor Qp12 and n-type MOS transistor Qn13 form one CMOS inverter, and the stored data is held in a circuit obtained by connecting these inverters in the form of a ring. The n-type MOS transistor Qn14 and the n-type MOS transistor Qn15 are transistors for controlling access from the bit line BL and the bit line /BL to the storage nodes. The read operation and the write operation of the stored data with respect to the storage nodes are similar to those of the binary CAM cell of FIG. 25 mentioned above, so the explanation of these operations will be omitted. Below, an explanation will be made of the mismatch search operation.
Note that, in this explanation, assume that the bit line BL is set at the high level and the bit line /BL is set at the low level when the search data has the logical value xe2x80x9c1xe2x80x9d and that levels inverse to those are set in the bit lines when the search data has the logical value xe2x80x9c0xe2x80x9d. Also, assume that the storage node N4 becomes the high level and the storage node N5 becomes the low level when the stored data of the CAM cell has the logical value xe2x80x9c1xe2x80x9d and that levels inverse to those are held in the storage nodes when the stored data has the logical value xe2x80x9c0xe2x80x9d.
When performing a match search between the stored data of the CAM cell and the search data, in the holding state of the stored data where the word line WL is set at the low level, either of the bit line BL or the bit line /BL is pulled down to the reference potential in accordance with the value of the search data, and the other is pulled up to the power supply voltage Vcc. Also, a constant current is supplied to the mismatch detection line ML by a not illustrated current supply circuit.
For example, when the search data input from the bit line has the logical value xe2x80x9c1xe2x80x9d and the stored data has the logical value xe2x80x9c0xe2x80x9d, the storage node N4 is at the low level, so the n-type MOS transistor Qn16 becomes off and the storage node N5 is at the high level, therefore the n-type MOS transistor Qn17 becomes on. Accordingly, the node N6 is connected to the bit line /BL of low level via the n-type MOS transistor Qn17, so the n-type MOS transistor Qn18 becomes off and the current flowing through the mismatch detection line ML is cut off.
When the search data has the logical value xe2x80x9c0xe2x80x9d and the stored data has the logical value xe2x80x9c1xe2x80x9d, the n-type MOS transistor Qn16 becomes on, the n-type MOS transistor Qn17 becomes off, and the node N6 is connected to the bit line BL of low level via the n-type MOS transistor Qn16, so the n-type MOS transistor Qn18 becomes off and the current flowing through the mismatch detection line ML is cut off.
When both of the search data and the stored data have the logical value xe2x80x9c1xe2x80x9d, the storage node N4 becomes the high level, so the n-type MOS transistor Qn16 becomes on and the storage node N5 becomes the low level, therefore the n-type MOS transistor Qn17 becomes off. At this time, the bit line BL is at the high level, so the node N6 becomes the high level, the n-type MOS transistor Qn18 becomes on, and the current of the mismatch detection line ML is not cut off.
When both of the search data and the stored data have the logical value xe2x80x9c0xe2x80x9d, the n-type MOS transistor Qn17 becomes on and the n-type MOS transistor Qn16 becomes off. At this time, the bit line /BL is at the high level, so the node N6 becomes the high level and the current of the mismatch detection line ML is not cut off.
In this way, the current of the mismatch detection line ML is cut off when the stored data and the search data do not match, while it is not cut off when the stored data and the search data match. Also, one type of NAND circuit is formed by the common mismatch detection line ML and n-type MOS transistors Qn18 of a plurality of CAM cells inserted in series on this. If there is even one CAM cell wherein the stored data and the search data do not match in these plurality of CAM cells, the current of the common mismatch detection line ML is cut off. Accordingly, by only searching for a mismatch detection line ML wherein the current is not cut off from among all mismatch detection lines ML of the CAM cell array, the address of the stored data matching with the search data can be searched for from among all stored data.
This concludes the explanation of the operation of the binary CAM cell shown in FIG. 26.
Next, an explanation will be made of a ternary CAM cell.
FIG. 27 is a circuit diagram of an example of the configuration of a ternary CAM cell having an SRAM type memory circuit.
In FIG. 27, notation Qp19, notation Qp21, notation Qp25, and notation Qp27 designate p-type MOS transistors, notation Qn20, notation Qn22 to notation Qn24, notation Qn26, and notation Qn28 to notation Qn34 designate n-type MOS transistors, notation WLa and notation WLb designate word lines, notation BL and notation/BL designate a pair of bit lines, notation SD and notation/SD designate a pair of search data lines, and notation ML designates the mismatch detection line.
In the p-type MOS transistor Qp19 and the n-type MOS transistor Qn20, the drain and source terminals are connected in series between the power supply voltage Vcc and the reference potential with a storage node N7 as the midpoint of connection. Also, both gates are connected to a storage node N8.
In the p-type MOS transistor Qp21 and the n-type MOS transistor Qn22, the drain and source terminals are connected in series between the power supply voltage Vcc and the reference potential with the storage node N8 as the midpoint of connection. Also, both gates are connected to the storage node N7.
In the n-type MOS transistor Qn23, the source and drain terminals are connected between the bit line BL and the storage node N7, and the gate is connected to the word line WLa.
In the n-type MOS transistor Qn24, the source and drain terminals are connected between a bit line /BL and the storage node N8, and the gate is connected to the word line WLa.
In the p-type MOS transistor Qp25 and the n-type MOS transistor Qn26, the drain and source terminals are connected in series between the power supply voltage Vcc and the reference potential with a storage node N9 as the midpoint of connection. Also, both gates are connected to a storage node N10.
In the p-type MOS transistor Qp27 and the n-type MOS transistor Qn28, the drain and source terminals are connected in series between the power supply voltage Vcc and the reference potential with the storage node N10 as the midpoint of connection. Also, both gates are connected to the storage node N9.
In the n-type MOS transistor Qn29, the source and drain terminals are connected between the bit line BL and the storage node N9, and the gate is connected to the word line WLb.
In the n-type MOS transistor Qn30, the source and drain terminals are connected between a bit line /BL and the storage node N10, and the gate is connected to the word line WLb.
In the n-type MOS transistor Qn31 and the n-type MOS transistor Qn33, the source and drain terminals are connected in series between the mismatch detection line ML and the reference potential with a node N11 as the midpoint of the connection. The gate of the n-type MOS transistor Qn31 is connected to the storage node N8, and the gate of the n-type MOS transistor Qn33 is connected to the search data line SD.
In the n-type MOS transistor Qn32 and the n-type MOS transistor Qn34, the source and drain terminals are connected in series between the mismatch detection line ML and the reference potential with a node N12 as the midpoint of the connection. The gate of the n-type MOS transistor Qn32 is connected to the storage node N9, while the gate of the n-type MOS transistor Qn34 is connected to the search data line /SD.
Next, an explanation will be made of the ternary CAM cell of FIG. 27 having the above configuration.
The ternary CAM cell shown in FIG. 27 has two memory circuits of the above six-transistor type SRAM cells. Three values are distinguished by the combination of the data having the logical value xe2x80x9c1xe2x80x9d or the logical value xe2x80x9c0xe2x80x9d stored in these two memory circuits.
Namely, a first memory circuit is formed by the p-type MOS transistor Qp19, n-type MOS transistor Qn20, p-type MOS transistor Qp21, n-type MOS transistor Qn22, n-type MOS transistor Qn23, and n-type MOS transistor Qn24. The access from a pair of bit lines to the storage node N7 and the storage node N8 is controlled by the n-type MOS transistor Qn23 and the n-type MOS transistor Qn24 becoming on or off in accordance with the level of the word line WLa. Also, a second memory circuit is formed by the p-type MOS transistor Qp25, n-type MOS transistor Qn26, p-type MOS transistor Qp27, n-type MOS transistor Qn28, n-type MOS transistor Qn29, and n-type MOS transistor Qn30. The access from a pair of bit lines to the storage node N9 and the storage node N10 is controlled by the n-type MOS transistor Qn29 and the n-type MOS transistor Qn30 becoming on or off in accordance with the level of the word line WLb.
The read and write operations of the data with respect to these first memory circuit and second memory circuit are similar to those of the memory circuit of the binary CAM cell mentioned above, so the explanation of these operations will be omitted. Below, an explanation will be made of the match search operation in a ternary CAM cell.
Note that, in the following concrete example, assume that the search data line SD is set at the high level and the search data line /SD is set at the low level when the search data has the logical value xe2x80x9c1xe2x80x9d and that the levels inverse to those are set in the bit lines when the search data has the logical value xe2x80x9c0xe2x80x9d. Also, assume that the storage node N7 and the storage node N9 become the high level and the storage node N8 and the storage node N10 become the low level when the stored data of the ternary CAM cell has the logical value xe2x80x9c1xe2x80x9d, the storage nodes become levels inverse to those when the stored data has the logical value xe2x80x9c0xe2x80x9d, and the storage node N8 and the storage node N9 become the low level and the storage node N7 and the storage node N10 become the high level in the case of the logical value xe2x80x9cxxe2x80x9d.
When carrying out a match search between the stored data of the CAM cell and the search data, in a state where the word line WLa and the word line WLb are deactivated to the low level, either of the search data line SD or search data line /SD is pulled down to the reference potential in accordance with the value of the search data, and the other is pulled up to the power supply voltage Vcc. Also, the mismatch detection line ML has been pulled up to the power supply voltage Vcc by a not illustrated voltage supply circuit.
For example, when the search data has the logical value xe2x80x9c1xe2x80x9d and the stored data has the logical value xe2x80x9c0xe2x80x9d, the storage node N8 becomes the high level and the n-type MOS transistor Qn31 becomes on and the storage node N9 becomes the low level and the n-type MOS transistor Qn32 becomes off. Also, the n-type MOS transistor Qn33 becomes on since the search data line SD is at the high level, and the n-type MOS transistor Qn34 becomes off since the search data line /SD is at the low level. Accordingly, the serial circuit of the n-type MOS transistor Qn31 and the n-type MOS transistor Qn33 becomes on and the mismatch detection line ML becomes the low level.
When the search data has the logical value xe2x80x9c0xe2x80x9d and the stored data has the logical value xe2x80x9c1xe2x80x9d, the serial circuit of the n-type MOS transistor Qn32 and the n-type MOS transistor Qn34 becomes on and the mismatch detection line ML similarly becomes the low level.
When both of the search data and stored data have the logical value xe2x80x9c1xe2x80x9d, the n-type MOS transistor Qn31 and the n-type MOS transistor Qn34 become off, so the mismatch detection line ML is held at the high level.
When both of the search data and stored data have the logical value xe2x80x9c0xe2x80x9d, both of the n-type MOS transistor Qn32 and the n-type MOS transistor Qn33 become off, so the mismatch detection line ML is similarly held at the high level.
Also, when the stored data of the ternary CAM cell has the logical value xe2x80x9cxxe2x80x9d, both of the storage node N8 and the storage node N9 become the low level, and both of the n-type MOS transistor Qn31 and n-type MOS transistor Qn32 become off. Accordingly, the mismatch detection line ML is held at the high level irrespective of the value of the search data.
In this way, the mismatch detection line ML becomes the low level when the stored data and the search data do not match, while it is held at the high level when the stored data and the search data match. Also, one type of NOR circuit is formed by the common mismatch detection line ML and n-type MOS transistor Qn31 to n-type MOS transistor Qn34 of a plurality of CAM cells connected in parallel to this. If there is even one CAM cell wherein the stored data and the search data do not match among these plurality of CAM cells, the common mismatch detection line ML becomes the low level. Accordingly, by judging the level of the mismatch detection line ML for every address corresponding to each word line, the address of the stored data matching with the search data can be searched for.
Further, when the logical value xe2x80x9cxxe2x80x9d is stored in the ternary CAM cell, irrespective of the value of the search data, the mismatch detection line ML is set at the high level, and it is judged that the search data and the stored data match.
This completes the explanation of the operation of the ternary CAM cell shown in FIG. 27.
Summarizing the disadvantages, when comparing the static noise margin (SNM) of SRAM cells, a four-transistor type SRAM cell, SNM tends to be smaller in SNM than a six-transistor type SRAM cell within the range of a low power supply voltage. When the SNM becomes small, the probability of destruction of the stored data of the memory cell due to noise rises, so there is the disadvantage of a degradation of the quality as a memory.
Accordingly, where the power supply voltage falls, the six-transistor type SRAM cell is frequently used, and therefore there are disadvantages such that the number of elements increases and a degree of integration falls, and the cost rises.
Also, a memory circuit comprised by the p-type MOS transistor Qp1, p-type MOS transistor Qp3, and the n-type MOS transistor Qn2 to n-type MOS transistor Qn6 in the CAM of FIG. 25 and similar memory circuits of FIG. 26 and FIG. 27 have configurations equal to that of a six-transistor type SRAM cell. In the binary CAM cell mentioned above, three further logical circuits are added to this six-transistor type SRAM cell, so 16 transistors become necessary as a whole in the ternary CAM cell. In this way, the CAM needs a larger number of elements in comparison with the usual RAM, so there is the disadvantage of a low degree of integration. Accordingly, it has been demanded that the number of elements in the CAM cell be decreased as much as possible and the degree of integration be improved.
A first object of the present invention is to provide a method of reading stored data in a semiconductor memory device capable of suppressing a fall of the SNM of a memory cell accompanying a fall of the voltage of the power supply, and a semiconductor memory device using the same method.
A second object is to provide a semiconductor memory device which can be comprised by a smaller number of elements in comparison with the related art.
To attain the above object, according to a first aspect of the present invention, there is provided a method of reading stored data of a semiconductor memory device which has a first storage node and a second storage node, a first transistor having a control terminal connected to the first storage node and having a pair of input/output terminals connected between the second storage node and a reference potential, a second transistor having a control terminal connected to the second storage node and having a pair of input/output terminals connected between the first storage node and the reference potential, a third transistor having a pair of input/output terminals connected between the first storage node and a first bit line and having a control terminal connected to a word line, and a fourth transistor having a pair of input/output terminals connected between the second storage node and a second bit line and having a control terminal connected to the word line, comprising the steps of applying a first voltage to the first bit line and the second bit line in a period for holding the stored data, and activating the word line and applying a second voltage higher than the first voltage to the first bit line and the second bit line at the time of reading the stored data.
According to the method of reading stored data in the first aspect of the present invention, in the period for holding the stored data, the first voltage is applied to the first bit line and the second bit line. At the time of reading the stored data, the word line is activated, and a second voltage higher than the first voltage is applied to the first bit line and the second bit line.
According to a second aspect of the present invention, there is provided a method of reading stored data of a semiconductor memory device having a plurality of memory cells arranged in a matrix, a plurality of word lines connected to memory cells of the same row of the matrix, and a plurality of first bit lines and second bit lines connected to memory cells of the same column of the matrix, wherein the memory cell has a first storage node and a second storage node, a first transistor having a control terminal connected to the first storage node and having a pair of input/output terminals connected between the second storage node and a reference potential, a second transistor having a control terminal connected to the second storage node and having a pair of input/output terminals connected between the first storage node and the reference potential, a third transistor having a pair of input/output terminals connected between the first storage node and a first bit line and having a control terminal connected to a word line, and a fourth transistor having a pair of input/output terminals connected between the second storage node and a second bit line and having a control terminal connected to the word line, comprising the steps of applying a first voltage to the first bit line and the second bit line in the period for holding the stored data and activating at least one of the plurality of word lines and applying a second voltage higher than the first voltage to the first bit line and the second bit line at the time of reading the stored data.
According to a third aspect of the present invention, there is provided a semiconductor memory device comprising a first storage node and a second storage node, a first transistor having a control terminal connected to the first storage node and having a pair of input/output terminals connected between the second storage node and a reference potential, a second transistor having a control terminal connected to the second storage node and having a pair of input/output terminals connected between the first storage node and the reference potential, a third transistor having a pair of input/output terminals connected between the first storage node and a first bit line and having a control terminal connected to a word line, a fourth transistor having a pair of input/output terminals connected between the second storage node and a second bit line and having a control terminal connected to the word line, and a control circuit for applying a first voltage to the first bit line and the second bit line in the period for holding the stored data and activating the word line and applying a second voltage higher than the first voltage to the first bit line and the second bit line at the time of reading the stored data.
According to the semiconductor memory device in the third aspect of the present invention, one memory circuit is comprised by the first transistor and the second transistor, and conduction between the first storage node of this memory circuit and the first bit line and conduction between the second storage node and the second bit line are controlled in accordance with an active/inactive state of the word line connected to the control terminals of the third transistor and the fourth transistor.
During the period for holding the stored data, the first voltage is applied to the first bit line and the second bit line by the control circuit.
At the time of reading the stored data, the word line is activated by the control circuit and, at the same time, a second voltage higher than the first voltage is applied to the first bit line and the second bit line by the control circuit. The stored data held in the first storage node and the second storage node are output via the third transistor and the fourth transistor to the first bit line and the second bit line.
According to a fourth aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of memory cells arranged in a matrix, a plurality of word lines connected to memory cells of the same row of the matrix, a plurality of first bit lines and second bit lines connected to memory cells of the same column of the matrix, and a control circuit for applying a first voltage to the first bit line and the second bit line in a period for holding the stored data and activating at least one of the plurality of word lines and applying a second voltage higher than the first voltage to the first bit line and the second bit line at the time of reading the stored data, wherein the memory cell has a first storage node and a second storage node, a first transistor having a control terminal connected to the first storage node and having a pair of input/output terminals connected between the second storage node and a reference potential, a second transistor having a control terminal connected to the second storage node and having a pair of input/output terminals connected between the first storage node and the reference potential, a third transistor having a pair of input/output terminals connected between the first storage node and the first bit line and having a control terminal connected to the word line, and a fourth transistor having a pair of input/output terminals connected between the second storage node and the second bit line and having a control terminal connected to the word line.
According to a fifth aspect of the present invention, there is provided a semiconductor memory device comprising a first storage node and a second storage node, a first transistor having a control terminal connected to the first storage node and having a pair of input/output terminals connected between the second storage node and a reference potential, a second transistor having a control terminal connected to the second storage node and having a pair of input/output terminals connected between the first storage node and the reference potential, a third transistor for controlling access with respect to the first storage node, a fourth transistor for controlling access with respect to the second storage node, a mismatch judgement circuit for judging a mismatch between the stored data in accordance with levels of the first storage node and the second storage node and the input search data, and a control circuit for setting the third transistor and the fourth transistor in a nonconductive state and applying a stored data holding voltage to the first storage node and the second storage node via the third transistor or the fourth transistor in a period of holding the stored data.
Preferably, the third transistor and the fourth transistor have a leakage current between input/output terminals larger in comparison with that of the first transistor and the second transistor.
According to the semiconductor memory device in the fifth aspect of the present invention, one memory circuit is formed by the first transistor, the second transistor, the third transistor, and the fourth transistor. In the period where the stored data of this memory circuit is held, the third transistor and the fourth transistor are set in the nonconductive state by the control circuit and, at the same time, a stored data holding voltage is applied to the first storage node and the second storage node via the third transistor or the fourth transistor. The leakage current of the third transistor and the fourth transistor is larger in comparison with that in the first transistor and the second transistor, so the stored data in accordance with the levels of the first storage node and the second storage node are held constant by this. The mismatch between the stored data held constant and the input search data is judged at the mismatch judgement circuit.
It is also possible if the control circuit sets the third transistor and the fourth transistor in the conductive state in the reading period of the stored data and, at the same time, apply a read voltage higher than the stored data holding voltage to the first storage node and the second storage node via the third transistor or the fourth transistor. By this, the static noise margin at the time of reading the stored data can be made larger.
According to a sixth aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of memory cells arranged in a matrix, a plurality of word lines connected to memory cells of the same row of the matrix, a plurality of mismatch detection lines connected to memory cells of the same row of the matrix, a plurality of first bit lines and second bit lines connected to memory cells of the same column of the matrix, and a control circuit for deactivating the word line and applying a stored data holding voltage to the first bit line and the second bit line in a period for holding the stored data of the memory cell, while deactivating the word line and applying voltage in accordance with input search data to the first bit line and the second bit line in a period for detecting mismatch between the search data and the stored data, wherein the memory cell has a first storage node and a second storage node, a first transistor having a control terminal connected to the first storage node and having a pair of input/output terminals connected between the second storage node and a reference potential, a second transistor having a control terminal connected to the second storage node and having a pair of input/output terminals connected between the first storage node and the reference potential, a third transistor having a pair of input/output terminals connected between the first storage node and the first bit line and having a control terminal connected to the word line, a fourth transistor having a pair of input/output terminals connected between the second storage node and the second bit line and having a control terminal connected to the word line, and a mismatch judgement circuit for judging a mismatch between the stored data in accordance with levels of the first storage node and the second storage node and the search data, and activating the mismatch detection line when mismatch is judged.
Preferably, the third transistor and the fourth transistor have a leakage current between input/output terminals larger in comparison with that of the first transistor and the second transistor.
According to a seventh aspect of the present invention, there is provided a semiconductor memory device comprising a first memory circuit and a second memory circuit each including a first storage node and a second storage node, a first transistor having a control terminal connected to the first storage node and having a pair of input/output terminals connected between the second storage node and a reference potential, a second transistor having a control terminal connected to the second storage node and having a pair of input/output terminals connected between the first storage node and the reference potential, a third transistor for controlling an access with respect to the first storage node, and a fourth transistor for controlling access with respect to the second storage node; a mismatch judgement circuit for judging mismatch between the stored data in accordance with the combination of data stored in the first memory circuit and the second memory circuit and the input search data; and a control circuit for setting the third transistor and the fourth drain in a nonconductive state, and applying a stored data holding voltage to the first storage node and the second storage node via the third transistor or the fourth transistor in a period of holding the stored data.
Preferably, the third transistor and the fourth transistor have a leakage current between input/output terminals larger than that of the first transistor and the second transistor.
According to the semiconductor memory device in the seventh aspect of the present invention, in the period where the stored data of the first memory circuit and the second memory circuit are held, the control circuit sets the third transistor and the fourth transistor in the nonconductive state and, at the same time, applies a stored data holding voltage to the first storage node and the second storage node via the third transistor or the fourth transistor. In the third transistor and the fourth transistor, the leakage current is larger in comparison with that of the first transistor and the second transistor, so the data of the first memory circuit and the second memory circuit held at the first storage node and the second storage node are held constant. The mismatch judgement circuit judges mismatch between the stored data of the combination of the data stored in the first memory circuit and the second memory circuit and the input search data.
It is also possible for the control circuit to set the third transistor and the fourth transistor in the conductive state in the reading period of the stored data and, at the same time, apply a read voltage higher than the stored data holding voltage to the first storage node and the second storage node via the third transistor or the fourth transistor. By this, the static noise margin at the time of reading the stored data can be made larger.
Also, preferably the device has a mismatch detection line, a first search data line and a second search data line, and a mismatch detection line voltage supply circuit for supplying voltage to the mismatch detection line; the mismatch judgement circuit includes a first activation circuit for activating the mismatch detection line in accordance with the level of the first storage node or the second storage node of the first memory circuit and the level of the first search data line, and a second activation circuit for activating the mismatch detection line in accordance with the level of the first storage node or the second storage node of the second memory circuit and the level of the second search data line; and the control circuit sets the third transistor and the fourth transistor in the nonconductive state and, at the same time, applies voltage in accordance with the search data to the first search data line and the second search data line in a period for detecting mismatch between the stored data and the search data.
According to an eighth aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of memory cells arranged in a matrix, a plurality of first word lines and second word lines connected to memory cells of the same row of the matrix, a plurality of mismatch detection lines connected to memory cells of the same row of the matrix, a plurality of first bit lines and second bit lines connected to memory cells of the same column of the matrix, a first search data line and a second search data line connected to memory cells of the same column of the matrix, and a control circuit for deactivating the first word lines and the second word lines, applying a stored data holding voltage to the first bit lines and the second bit lines, and applying voltage in accordance with the search data to the first search data line and the second search data line in a period for detecting mismatch between the input search data and the stored data of the memory cell, wherein the memory cell includes a first memory circuit connected to the first word line, a second memory circuit connected to the second word line, and a mismatch judgement circuit for judging mismatch between the stored data in accordance with the combination of data stored in the first memory circuit and the second memory circuit and the search data, and activating the mismatch detection line when judging mismatch; the first memory circuit and the second memory circuit each include a first storage node and a second storage node, a first transistor having a control terminal connected to the first storage node and having a pair of input/output terminals connected between the second storage node and a reference potential, a second transistor having a control terminal connected to the second storage node and having a pair of input/output terminals connected between the first storage node and the reference potential, a third transistor having a pair of input/output terminals connected between the first storage node and the first bit line and having a control terminal connected to the first word line or the second word line, and a fourth transistor having a pair of input/output terminals connected between the second storage node and the second bit line and having a control terminal connected to the first word line or the second word line.
Preferably, the third transistor and the fourth transistor have a leakage current between input/output terminals larger in comparison with that of the first transistor and the second transistor.
According to a ninth aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of memory cells arranged in a matrix, a plurality of word lines connected to memory cells of the same row of the matrix, a plurality of mismatch detection lines connected to memory cells of the same row of the matrix, a plurality of first bit line pairs and second bit line pairs connected to memory cells of the same column of the matrix, a first search data line and a second search data line connected to memory cells of the same column of the matrix, and a control circuit for deactivating the word lines, applying a stored data holding voltage to the first bit line pairs and the second bit line pairs, and applying voltage in accordance with the search data to the first search data line and the second search data line in a period for detecting mismatch between the input search data and the stored data of the memory cell, wherein the memory cell includes a first memory circuit connected to the first bit line pair, a second memory circuit connected to the second bit line pair, and a mismatch judgement circuit for judging mismatch between the stored data in accordance with the combination of data stored in the first memory circuit and the second memory circuit and the search data, and activating the mismatch detection line when judging mismatch; the first memory circuit and the second memory circuit each include a first storage node and a second storage node, a first transistor having a control terminal connected to the first storage node and having a pair of input/output terminals connected between the second storage node and a reference potential, a second transistor having a control terminal connected to the second storage node and having a pair of input/output terminals connected between the first storage node and the reference potential, a third transistor having a pair of input/output terminals connected between one bit line of the first bit line pair or the second bit line pair and the first storage node and having a control terminal connected to the word line, and a fourth transistor having a pair of input/output terminals connected between the other bit line of the first bit line pair or the second bit line pair and the second storage node and having a control terminal connected to the word line.
Preferably, the third transistor and the fourth transistor have a leakage current between input/output terminals larger in comparison with that of the first transistor and the second transistor.